Ji, Z and Zhang, JF and Zhang, WEI and Zhang, X (2014) A single device based Voltage Step Stress (VSS) Technique for fast reliability screening. In: Reliability Physics Symposium, 2014 IEEE International . GD.2.1-GD.2.4. (Reliability Physics Symposium, 2014, 1st - 5th June 2014, Waikoloa, HI).
IRPS-Lifetime-clean version - v2.pdf - Accepted Version
A new wafer-level reliability qualification methodology is proposed. Unlike conventional method which usually takes days to completion, the total test time of the new technique can be shortened within 2 hours. Besides, it only requires a single device. This new technique is easy to implement on commercial equipment and it has been successfully validated on different processes including the most advanced 28nm process with both SiON and high-k gate stacks. This new technique can be an effective tool for fast reliability screening during process development in future.
|Item Type:||Conference or Workshop Item (Paper)|
|Subjects:||Q Science > QC Physics
T Technology > TK Electrical engineering. Electronics. Nuclear engineering
|Divisions:||Electronics and Electrical Engineering|
|Date Deposited:||09 Oct 2015 11:19|
|Last Modified:||09 Oct 2015 11:19|
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