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SrTiO3 for sub-20 nm DRAM technology nodes — characterization and modeling

Ji, Z (2015) SrTiO3 for sub-20 nm DRAM technology nodes — characterization and modeling. In: Microelectronic Engineering , 147 (C). pp. 126-129. (IEEE Semiconductor Interfaces Specialist Conference, 1st - 5th December 2014, San Diego, CA).

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Abstract

The electrical properties of Ru/SrTiOx/Ru capacitors have been investigated. Equivalent Oxide Thickness (EOT) of 0.38 nm at 0 V and current density of 10−7 A cm−2 at ±1 V and 25 °C meet the sub-20 nm DRAM requirements. Relaxation measurements were performed, indicating acceptable charge loss. Modeling of charge trapping at defect sites based on multi-phonon trap-assisted-tunneling quantitatively well describes leakage and capacitance behavior.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering
Divisions: Electronics and Electrical Engineering
Publisher: Elsevier
Date Deposited: 09 Oct 2015 12:43
Last Modified: 09 Oct 2015 12:43
URI: http://researchonline.ljmu.ac.uk/id/eprint/2148

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