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NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

Ji, Z and Gao, R and Manut, AB and Zhang, JF and Franco, J and Hatta, SWM and Zhang, W and Kaczer, B and Linten, D and Groeseneken, G NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling. IEEE Transactions on Electron Devices. ISSN 0018-9383 (Accepted)

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Abstract

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the 15 accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process.

Item Type: Article
Additional Information: (c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
Uncontrolled Keywords: 0906 Electrical And Electronic Engineering
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering
Divisions: Electronics and Electrical Engineering
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Date Deposited: 24 Aug 2017 10:04
Last Modified: 24 Aug 2017 10:04
URI: http://researchonline.ljmu.ac.uk/id/eprint/6980

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