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A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

Zheng, X, Zhang, C, Lv, F, Zhao, F, Yuan, S, Yue, S, Wang, Z, Li, F, Wang, Z and Jiang, H (2017) A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 52 (11). pp. 2963-2978. ISSN 0018-9200

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Abstract

This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip communications in a 65-nm CMOS process. The TX implements a quarter-rate multi-multiplexer (MUX)-based four-tap feed-forward equalizer (FFE), where a charge-sharing-effect elimination technique is introduced into the 4:1 MUX to optimize its jitter performance and power efficiency. The RX employs a two-stage continuous-time linear equalizer as the analog front end and integrates a low-cost sign-based zero-forcing engine relying on edge-data correlation to automatically adjust the tap weights of the TX-FFE. By embedding low-pass filters with an adaptively adjusting bandwidth into the data-sampling path and adopting high-linearity compensating phase interpolators, the clock data recovery achieves both high jitter tolerance and low jitter generation. The fabricated TX and RX chipset delivers 40-Gb/s PRBS data at BER <; 10-12 over a channel with >16-dB loss at half-baud frequency, while consuming a total power of 370 mW.

Item Type: Article
Additional Information: © 2017 IEEE in additional information box
Uncontrolled Keywords: 0906 Electrical And Electronic Engineering
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering
Divisions: Computer Science
Publisher: IEEE
Related URLs:
Date Deposited: 24 Sep 2018 08:53
Last Modified: 24 Sep 2018 08:56
DOI or Identification number: 10.1109/JSSC.2017.2746672
URI: http://researchonline.ljmu.ac.uk/id/eprint/9304

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