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On the understanding of PMOS NBTI degradation in advance nodes: Characterization, modeling and exploration on the physical origin of defects

Xue, Y, Ren, P, Wu, J, Liu, Z, Wang, S, Li, Y, Wang, Z, Sun, Z, Wang, D, Wen, Y, Xia, S, Zhang, L, Zhang, J, Ji, Z, Luo, J, Deng, H, Wang, R, Yang, L and Huang, R (2023) On the understanding of PMOS NBTI degradation in advance nodes: Characterization, modeling and exploration on the physical origin of defects. IEEE Transactions on Electron Devices, 70 (9). pp. 4518-4524. ISSN 0018-9383

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A complete separation flow for different types of traps, including the separation of energy levels (ETs) and the separation of charging kinetics, making different traps can be modeled and characterized separately by simple experiments. Industrial-grade 7 nm pFinFETs under negative bias temperature instability (NBTI) stress condition is chosen for the demonstration. Four types of traps are identified, including oxide trap Type-A located in the interfacial layer (IL) layer, oxide trap Type-B (B1 and B2) located in the HK layer, and interface trap Type-C located at Si/IL interface. Type-A trap belongs to a preexisting trap which can be well described by the two-state non-radiative multiphonon (NMP) theory and may originate from Vo in SiO<inline-formula> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula>. Types-B1 and Type-B2 traps originate from Ni and Hi respectively, and can be described by incorporating the activation state into the two-state NMP theory. Type-C is located at Si/IL interface and follows the classical power law relationship with the time exponent of 0.17, which may be caused by the breakage of the Si-H bonds due to the reaction with atomic H from either the substrate or the gate. By modeling each type of trap respectively, a unified aging prediction framework was proposed and its long-term predictive capability was experimentally verified under various working conditions. The contribution of each trap to degradation is also discussed, which is helpful to the Design-Technology co-optimization (DTCO) in advanced nodes.

Item Type: Article
Additional Information: © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works
Uncontrolled Keywords: 0906 Electrical and Electronic Engineering; Applied Physics
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Engineering
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
SWORD Depositor: A Symplectic
Date Deposited: 11 Sep 2023 14:01
Last Modified: 11 Sep 2023 14:01
DOI or Identification number: 10.1109/TED.2023.3294460
URI: https://researchonline.ljmu.ac.uk/id/eprint/21414

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