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ESD characterization of planar InGaAs devices

Ji, Z, Linten, D, Boschke, R, Hellings, G, Chen, SH, Alian, A, Zhou, D, Mols, Y, Ivanov, T, Franco, J, Kaczer, B, Zhang, X, Gao, R, Zhang, JF, Zhang, WD and Collaert, N (2015) ESD characterization of planar InGaAs devices. In: Reliability Physics Symposium (IRPS), 2015 IEEE International . 3F.1.1-3F.1.7. (IEEE International Reliability Physics Symposium (IRPS), 19th April - 23th April 2015, Monterey, CA).

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We present a comprehensive study of ESD reliability (TLP) on planar nMOSFETs with In0.53Ga0.47As as the channel material. Two types of traps are found during ESD stress. They are formed through independent mechanisms: transient Ef-lowering induced pre-existing e-traps discharging in the gate stack and hot hole induced e-traps generation through impact ionization in the InP buffer. These two types of traps explain the observed walk-out of off-state channel leakage current as well as the two-stage current conduction phenomena in the TLP measurement. The generated e-traps are permanent and can introduce detrimental conduction current harmful to the device performance. By properly selecting the buffer material, these defects can be removed.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering
Divisions: Electronics & Electrical Engineering (merged with Engineering 10 Aug 20)
Publisher: IEEE
Date Deposited: 09 Oct 2015 10:44
Last Modified: 13 Apr 2022 15:14
URI: https://researchonline.ljmu.ac.uk/id/eprint/2144
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