A Space Vector PWM Technique for a Three-Level Symmetrical Six-Phase Drive

A space vector pulse-width modulation (SVPWM) algorithm for a three-level symmetrical six-phase drive, based on a vector space decomposition approach, is, for the first time, presented and experimentally proven in this paper. The process how to correctly select the optimal switching sequences, based on several starting requirements and conditions for the analyzed topology, such that the output phase voltage waveforms do not contain any low-order harmonics, is explained in detail. The developed SVPWM algorithm is verified experimentally using a three-level neutral-point-clamped converter and a symmetrical six-phase induction machine. Obtained results prove the validity of the developed SVPWM algorithm. The performance of the SVPWM algorithm is compared with the corresponding carrier-based modulation strategy, and it is shown that the two techniques yield identical performance. Finally, both simulation and experimental analysis of the voltage and current total harmonic distortion (THD) are reported.


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Abstract-A space vector pulse-width modulation (SVPWM) algorithm for a three-level symmetrical sixphase drive, based on vector space decomposition (VSD) approach, is for the first time presented and experimentally proven in this paper. The process how to correctly select the optimal switching sequences, based on several starting requirements and conditions for the analysed topology, such that the output phase voltage waveforms do not contain any low order harmonics, is explained in detail. The developed SVPWM algorithm is verified experimentally using a three-level neutral-pointclamped (NPC) converter and a symmetrical six-phase induction machine. Obtained results prove the validity of the developed SVPWM algorithm. The performance of the SVPWM algorithm is compared with the corresponding carrier-based modulation strategy and it is shown that the two techniques yield identical performance. Finally, both simulation and experimental analysis of the voltage and current THD are reported.

I. INTRODUCTION
ULTILEVEL inverter supplied multiphase drives have been gaining interest of researchers and industries in recent years. The utilisation of power electronic converters to supply the machine contributes to a possibility of allowing the motor current to be shared between more than three machine phases. This reduces the current rating of the power semiconductors used in the inverter, when compared to the conventional three-phase case [1]. An ac machine with a number of phases, n, larger than three is known as a multiphase machine. Although there are studies discussing the machines with prime numbers of phases, such as five or seven [2][3][4][5], they are rarely used in practice since they have to be custom made. On the other hand, machines with six or nine phases can be obtained by simply rewinding the stator of the widely available three-phase machines. This utilises the original frame and stator/rotor laminations of the three-phase machines and thus saves on the manufacturing cost.
In addition, the usage of multilevel inverters also enables further increase in the possible number of inverter output voltage levels, l, by adapting different power electronic converter topologies such as neutral-point clamped (NPC) inverter introduced in [6]. The NPC inverter topology was proposed with the aim to reduce the magnitude of the harmonics which cause losses and pulsating torque in medium power drives, while at the same time permitting the controllability of the fundamental output phase voltage [6]. As l increases, the output phase voltage waveforms approach more and more sinusoidal waveforms, hence reducing the total harmonic distortion (THD) [7]. Furthermore, multilevel inverters can sustain much higher dc-link voltage compared to the conventional two-level inverters with the usage of the power semiconductors of the same rating [8]. This enables realisation of high power drives using the existing power semiconductors of limited ratings. Therefore, on one hand, it seems reasonable to increase both n and l, thus attaining the benefits of both approaches. On the other hand, since the space vector modulation algorithm depends on n and l, the process of determining the right switching sequences for multiphase multilevel topologies becomes more complex. Nevertheless, as it will be shown in this paper, the implementation of the SVPWM strategy in practice is rather simple.
The modulation strategy for a multilevel multiphase drive is investigated and presented for the first time in [5], based on analysis of a three-level NPC inverter driving a five-phase induction motor. Since then, several papers have been published presenting new modulation methods that can be implemented in multilevel multiphase drives [2][3][4][9][10][11][12]. The algorithms [9][10][11][12] are similar to the matrix implementation of carrier-based PWM and do not analyse projections of the vectors into the planes. Hence, these algorithms are not considered here as 'classical' space vector algorithms. The first successful implementation of a multilevel multiphase SVPWM algorithm, based on the VSD approach [13], which is considered as a classical SVPWM approach, is presented in [4]. The algorithm was developed for a three-level five-phase drive. In [2], the modulation strategy is then adapted and optimised with the aim of reducing the variation of common mode voltage (CMV). In addition, a comparison in terms of performance between SVPWM and carrier-based PWM strategies is also discussed in [2]. It is proven that the optimised SVPWM algorithm yields the same results as inphase disposition carrier-based modulation strategy (PD-PWM) applied to sinusoidal references with 'double min-max injection'. Furthermore, the concept of optimised SVPWM strategy is later adapted and successfully applied to a threelevel seven-phase NPC inverter in [3]. This paper builds on [14], where basic principles of the SVPWM algorithm for a three-level symmetrical six-phase drive, based on the VSD approach, were introduced. In [14], the developed algorithm was evaluated purely by simulation and without considering some practical aspects, such as dead time. In this paper, the SVPWM algorithm is for the first time implemented and validated experimentally. Furthermore, since a PWM strategy for a three-level NPC inverter, regardless of the number of phases, can easily be realised using PD-PWM with 'double min-max injection' [2,15,16], a performance comparison between the SVPWM and PD-PWM in terms of the voltage and current THD, as well as execution time, is also reported in this paper.
The outline of this paper is as follows. In Section II, the proposed SVPWM algorithm, introduced in [14], is revisited. Practical implementation of developed SVPWM algorithm is summarized in Section III. Obtained results prove the validity of the developed SVPWM algorithm. Furthermore, the behaviour of the developed SVPWM algorithm is compared with the PD-PWM in the same section. Identical performance is demonstrated. Finally, Section IV concludes the work.

II. SPACE VECTOR PWM ALGORITHM
SVPWM for each number of levels and phases is unique, although it may follow the same general directions as in [2][3][4]. Topology considered in this paper is a standard three-level NPC VSI supplying a symmetrical six-phase induction machine with sinusoidally distributed windings and a single neutral point (see Fig. 1). The desired output phase voltages are sinusoidal. Since the stator windings of a symmetrical sixphase machine are spatially shifted by 2π/6, the desired output phase voltages, v * phk, can be defined as: where k = 1 to 6, which also corresponds to phase a to f. It should be noted that these waveforms will also serve as the reference waveforms for the developed SVPWM algorithm. Although sinusoidal output phase voltages are desired, the actual end results of any applied PWM algorithm are switching sequences which will be applied for specific duration of time to the inverter switches. These switching sequences are actually gating signals, which in turn generate the inverter output leg voltages. The output leg voltages are referenced to the negative dc-bus rail of the NPC converter (NDC). The relationship between the output phase voltage, vphk and the output leg voltage, vLEGk is given with: The second term of (2) represents CMV (potential difference between load neutral point and NDC), which is a scalar value. Therefore, it is obvious from (2) that, at each instant of time, the order of the vphk waveforms is the same as the order of vLEGk waveforms [3]. The aim of the SVPWM algorithm, developed here, is to select and correctly apply the switching sequences, such that the inverter voltages, vLEGk, are sinusoidal on average, which subsequently will generate sinusoidal vphk waveforms.
Based on the combination of inverter switches, four possible vLEGk levels can be obtained per inverter leg. However, one of the possible levels yields a high impedance at the output, which will not be considered further in the developed SVPWM algorithm. The other three levels are: 0, Vdc/2 and Vdc (when referred with respect to NDC). Furthermore, these vLEGk levels can be denoted as 0, 1 and 2, respectively, when normalised by Vdc/2. Thus, for the analysed three-level six-phase topology there are 3 6 = 729 possible switching states, which will be denoted further as 0 to 728. If normalised notation of vLEGk is used, these possible switching states can also be represented in six-digit ternary numeral system as 000000 to 222222, respectively.

A. Voltage Space Vector Projections
Based on the VSD approach [13], the space vector projections of the phase voltages can be realized using transformation matrix: where α = 2π/6 for a symmetrical six-phase machine. This transformation matrix also applies to any set of symmetrical six-phase variables, e.g. leg voltages vLEGk, output phase currents, iphk, etc. It is clear from (3) that the space vectors are projected into two mutually orthogonal two-dimensional planes, α-β and x-y, and two zero-component axes, 0 + and 0 -.
By substituting the leg (phase) voltages into (3), the projections of the leg (phase) voltage space vectors into these planes and axes are obtained. It can be shown that the space vector projections into the α-β and x-y plane, as well as onto 0axis, of phase and leg voltages, are identical. With regard to the 0 + axis, the phase voltage space vector projection is zero, while for the leg voltage space vectors it is not. In fact, the projection of the leg voltage space vectors onto 0 + axis represents CMV. Therefore, it is possible to realise sinusoidal vphk waveforms by means of vLEGk space vectors if 0 + axis is not considered. That is normally done in all SVPWM algorithms although the proper explanation is usually omitted. The same is applied here, so the 0 + axis (i.e. CMV) is not considered further in the developed SVPWM algorithm. In This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. other words, CMV is not controlled and it will be just a consequence of the selection of the switching states. It can be shown that the low order harmonics of the order 6k ± 1 (k = 0, 1, 2, 3…) of phase voltage space vectors map into the α-β plane whereas the low order harmonics of the order 6k ± 2 (k = 0, 1, 2, 3…) and 3k (k = 1, 3, 5…) map into the x-y plane and 0axis, respectively. From the machine (i.e. load) point of view, the low order harmonics, which map into α-β plane, contribute to the torque (producing torque ripple), while the low order harmonics that map into x-y plane and 0axis produce only losses [17]. Moreover, one finds that, by putting (1) into (3), the reference phase voltage space vector in the α-β plane travels at angular speed ω and has a magnitude of V * , thus forming a circular trajectory. On the contrary, the projections of phase voltage space vector in the x-y plane, 0 + and 0axes are zero. In other words, in order to achieve the desired sinusoidal phase voltage waveforms, the average values of x-y and 0components must be controlled to zero, i.e. the low order harmonics that correspond to the x-y plane and 0axis must be zeroed. This will be one of the main requirements for the developed SVPWM algorithm.

B. Reduction of the Number of Possible Switching States
As stated previously, there are 729 possible switching states and they correspond to 3 6 -2 6 = 665 phase voltage space vectors [18]. This indicates that several switching states generate identical projection of space vectors, thus causing redundancies. However, not all space vectors can be utilised to generate sinusoidal vphk waveforms [4]. These space vectors can be eliminated by implementing the order-per-sector law [4]. This simplifies the process of selecting proper space vectors for the switching sequences. In essence, the order-persector law implies that the possible switching states must follow the order of the v * phk waveforms in their respective sectors in the α-β plane [2][3][4].
The sector angle, θ, in the α-β plane corresponds to the phase 'a' phase angle, i.e. θ=ωt. Therefore the angular borders between the sectors correspond to the phase angle at which the mutual order of the sinusoidal v * phk waveforms changes, i.e. at every π/6 radians for a symmetrical six-phase case. Thus, the projected switching states in each sector are compared to their respective order of sinusoidal v * phk waveforms. The projected switching states which do not meet the conditions of the orderper-sector law are discarded. As an example, the switching state 407 (120002), which is projected into the first sector (S1) (i.e. 0 ≤ θ < π/6) in the α-β plane, does not meet the stated condition. This is because the order of v * phk waveforms in S1 is while for switching state 407 the vA is less than vB (1<2, i.e. Vdc/2<Vdc). Thus it is discarded. By implementing the order-per-sector law to all sectors, the numbers of possible switching states and voltage space vectors are significantly reduced, from 729 to 189 and from 665 to 157, respectively. The projections of the remaining voltage space vectors into the α-β are shown in Fig. 2 (decimal representation is used). In order to acquire the switching state of each leg, conversion from decimal to ternary numeral representation should be done. For projections into x-y plane and onto 0axis please refer to [14].

C. Determination of the Potential Switching Sequences
Once reduction of the number of switching states is done, complete potential switching sequences can be determined more easily. In order to achieve sinusoidal vphk waveforms, the potential switching sequences have to meet several requirements and satisfy several desirable conditions. As mentioned previously, one of those requirements is that the average values of x-y and 0components must be zero, so that the low order harmonics which correspond to the x-y plane and 0axis do not exist. Also, the number of the chosen space vectors in the switching sequences must be the same as the number of machine's phases [19], i.e. six here. In addition, it is desirable that the transition of inverter leg voltages is symmetrical in one switching period, i.e. in the first half of the switching period vLEGk increases when transiting level and in the other half the level in transition decreases. Moreover, in order to minimise losses and reduce dv/dt, it is desirable that the level increment of vLEGk is only one, either increasing or decreasing during the transition [20]. Furthermore, the chosen starting (i.e. the first) switching states for the switching sequences should only comprise either 'ones' or 'zeros', or combination of both in six-digit ternary number representation [2]. This is so since in the first half of the switching period it is desirable that the inverter vLEGk level increases by one level. Since the maximum achievable vLEGk level is two, the switching states which contain 'two' (in six-digit ternary numeral system), cannot be chosen as potential starting switching states.
The process of determining the potential switching sequences begins by choosing the potential starting switching states. As an example, among 28 switching states in S1 (including those at the borders with the second, S2, and the twelfth, S12, sector), only seven switching states can be chosen as potential starting switching states. These switching states are shown within red boxes in Fig. 2. In fact, each sector has seven potential starting switching states. After the potential starting switching states are selected, the This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. corresponding potential switching sequences are chosen such that each inverter leg voltage, vLEGk, increases by one level during the first half of the switching period. Each increment of a certain inverter leg voltage in a switching sequence corresponds to a certain transition of the space vector in the αβ and x-y planes, as well as 0axis. As an example, all possible transitions of voltage space vectors in S1 are illustrated with different colour of arrows in Fig. 3 (increment of: vA = orange, vB = blue, vC = green, vD = red, vE = cyan and vF = purple). When all possible switching state transitions are identified, the switching sequences should be determined. As already mentioned, each switching sequence should satisfy a requirement that switching occurs in each leg and that in the first half of the switching period a one-level increasing transition occurs. Graphically that means that starting from a potential starting switching state six-angle space vector transition pattern, formed of six arrows (all of a different colour), should be created. These six transitions of voltage space vectors result in seven switching states per switching sequence. However, two of the switching states (the first and the seventh) yield identical space vector projections. Therefore, the number of the chosen space vectors in a switching sequence remains as six (which satisfies one of the previously stated requirements). All issues being considered, one can find that there are 64 potential switching sequences in each sector. These 64 switching sequences can be categorised into 32 unique space vector transition patterns. Furthermore, one can see that some transition patterns encompass several potential starting switching states, which indicates the existence of redundancy in the switching sequences. As an example, in S1, switching sequences 110001-111001-211001-221001-221011-221111-221112 and 110000-110001-111001-211001-221001-221011-221111 are clearly different, but they produce an identical space vector transition pattern (highlighted in grey in Fig. 3) in the α-β and x-y planes, as well as in 0axis. This shows the existence of switching sequence redundancies.
Although there are 32 space vector transition patterns in each sector, not all of them meet the requirement that the average values of x-y and 0components must be zero. In order to single out those transition patterns (and hence corresponding switching sequences), a graphical method of analysis of the space vector transition patterns of those potential switching sequences [2,4], is implemented next. The graphical method for elimination considers projection of the states in the x-y plane and 0axis: if all states are located at one side of the line crossing the origin, i.e. on one side of the 0axis, that space vector transition pattern cannot lead to zero on average in that plane, i.e. axis. Hence, those patterns and corresponding sequences can be eliminated. By graphically analysing the corresponding transition patterns in the x-y plane, one can see that only eight out of 32 transition patterns surround the origin, and are thus capable of achieving zero value in the x-y plane on average. Likewise, in 0axis, another two out of the eight remaining transition patterns are identified such that the average value of 0components cannot be zero. As a result, only six transition patterns (which also correspond to 20 potential switching sequences due to the redundancy in the switching sequences) are left per sector.

D. Dwell Time Calculation and Sector Division
The duration of the applied space vector in any chosen switching sequence is commonly known as dwell time. The dwell times of applied space vectors within a switching sequence can be calculated based on the volt-second balance principle and time balancing equation, as in: where v * represents a six-dimensional space vector of the v * phk waveforms (k = 1, 2, .., 6), vk are the six chosen sixdimensional space vectors with corresponding projections in the α-β, x-y and 0 + , 0axes, Ts is the switching period and Tk are the dwell times of the applied space vectors. Next, (4) and (5) can be rearranged into a matrix form as: s y x y y y y y y   This work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/3.0/. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
The 0 + axis is not considered in the developed SVPWM algorithm. Hence, the fifth row in (6), which is supposed to represent the 0 + axis, is replaced by (5). This ensures that the sum of calculated dwell times equals Ts. In addition, it is also desirable for the calculated dwell time of the first space vector to be equally shared between the first and the seventh switching state, so that the best possible quasi-circular flux trajectory can be achieved in the α-β plane [15]. Since the dwell times are calculated based on space vector projections, each of six transition patterns will yield different values of dwell times. However, the calculated dwell times for a transition pattern remain the same for all redundant switching sequences associated to this transition pattern [3].
Since the desired projections of reference phase voltage space vector in the x-y plane and 0axes are zero, while in the α-β plane the projections of the reference phase voltage space vector represent desired sinusoidal phase voltages, the v * x, v * y and v * 0-are set to zero in (6), while v * α and v * β are set to V * cos(ωt) and V * sin(ωt), respectively. Furthermore, one can see that the solutions for dwell time calculation for each transition pattern only exist solely in certain regions (commonly known as region of application) in a sector. This results in the division of the sector into six sub-sectors. Although these regions of application can be determined using analytical calculations [4], the method based on visualising the numerical solutions of the calculated dwell times [3] is adopted in this paper. The dwell times of each transition pattern, based on (6), are repetitively calculated in Matlab by gradually increasing the value of V * for v * α and v * β from zero to 2/3Vdc (governed by the largest hexagon in the α-β plane). If the solution for dwell times exists for that particular phase voltage space vector reference, a dot is plotted at its projected location in the α-β plane. Hence, the regions of application corresponding to each transition pattern can be visually determined. As an example, the transition pattern highlighted in grey in Fig. 3 forms a region of application shown (with dots) in Fig. 4. The regions of application that correspond to the six transition patterns in S1 are denoted by A1 to F1. Similarly, the division of other sectors into sub-sectors can also be done, as indicated for S2 in Fig. 4.

E. Potential Switching Sequences Optimisation
The existence of switching sequence redundancies in some transition patterns offers flexibility in choosing the optimal switching sequences. However, the optimal switching sequences must be chosen such that the transition of leg voltage levels between sub-sectors is minimised, since this minimises the switching losses [15]. Also, it is desirable to have more than one of the inverter legs connected to the neutral point, i.e. vLEGk equal to Vdc/2. This offers more options in properly balancing the dc-link capacitor voltages [4]. In this way the final six out of 20 switching sequences per sector, corresponding to the transition patterns, are selected. As an example, the optimal switching sequences for S1 are listed in Table I. Only switching states in the first half of the switching period are listed, since the order is reversed in the second half.

F. Sub-sector Determination
As the reference phase voltage space vector travels in the α-β plane, it moves through the sectors and sub-sectors. Therefore, the location of the reference phase voltage space vector plays a crucial role in defining the sub-sector and hence the relevant switching sequence which should be applied [4]. Thus, one finds that the borders of the sub-sectors can function as the limits to where the reference phase voltage space vector is currently located. In other words, by projecting these borders onto several perpendicular axes, and comparing them with the projection of the projected reference phase voltage space vector onto the same axes, the corresponding sub-sector can be determined. As an example, an illustration of how this is implemented for S1 is shown in Fig. 5. As can be seen in Fig. 5, the sub-sectors are divided by five borders. These borders can be projected onto four perpendicular axes, denoted as P1 to P4. The distances of these projected borders, on the respective axes, to the origin (they will be referred to further as limits and denoted as L1 to L5), are then calculated. One gets that L2 = L4 = 0.25Vdc, L1 = L3 = 3 /6Vdc and L5 = 0.5Vdc. Likewise, the lengths which are associated to the projections of the reference phase voltage space vector onto the same perpendicular axes, denoted as V * 1 to V * 4, are also calculated and then compared with their respective limits. By satisfying the conditions set by the limits, the right sub-sector can be identified. Consequently, the corresponding switching sequence is applied.
The sub-sectors of the even and odd sectors are mirror images of each other, as can be seen from Fig. 4. One can see that not only the four perpendicular axes, P1 to P4, and the projected borders on the respective axes are mirrored, even the lengths of the projected borders L1 to L5 are also mirrored and retain their values. In other words, the conditions which define the location of the projected reference phase voltage space vector and consequently determine the relevant sub-sectors, are the same for all sectors. Moreover, by mapping the rest of the sectors onto S1 and S2, one finds that the length of the reference phase voltage space vector projections onto their respective perpendicular axes can be generalised as: Fig. 4: Regions of application in S1 and S2 (region of application for shaded transition pattern from Fig. 3 is plotted by dots generated by Matlab code). This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

III. EXPERIMENTAL RESULTS
Although the selection process to obtain the optimal switching sequences is complex, the final implementation of the developed SVPWM algorithm is rather simple. As mentioned previously, due to the symmetry of the sub-sector division (see Fig. 4), the other odd and even sectors (including their respective sub-sectors) can be mapped onto S1 and S2, respectively. In other words, the switching sequences of other sector sub-sectors can be generated from the selected switching sequences for the S1 and S2 sub-sectors. To demonstrate this, let us take as an example switching states 649 in S1 (i.e. in the first sector pair SP1), and 153 in S5 (i.e. in the third sector pair SP3), which are located at the same positions within these sectors (see Fig. 2). Using ternary numeral system 649 and 153 can be represented as: 220001 and 012200, respectively. One can see that 012200 in SP3 can be obtained from switching state 220001 in SP1, by circularly rotating elements to the right by two (3-1=2) places. Thus, switching states and hence sequences in any other sector pair can be easily generated based on those in SP1. It should also be noted that, by simple manipulation, it is possible to generate S2 and other sector sub-sector switching sequences from only S1 selected switching sequences (refer to Table I). Thus, one gets that the essential components required for developing the modulator of the algorithm are: 1) the method to precisely determine the location of the reference phase voltage space vector projection and the relevant switching sequence which is generated by mapping the corresponding sub-sector with respect to S1 and S2 sub-sectors; and 2) the dwell time calculation of the respective switching sequences. Since the calculated dwell times are associated with the transition patterns, i.e. sub-sectors, it is possible to use the precalculated inverse matrix values [as in (6)], and, based on the switching sequences of S1 and S2 sub-sectors, to calculate the dwell times of the other odd and even sectors' sub-sectors [3]. In the current implementation of the algorithm switching sequences for all sub-sectors in S1 and S2 as well as corresponding pre-calculated inverse matrix values are stored in the memory. In this way, memory usage is sacrificed for the sake of reduction of the execution time of the algorithm. Block diagram illustrating the implementation of the proposed algorithm is shown in Fig. 6. Although a rapid control prototyping system (dSpace) was used for real-time implementation of the algorithm, block diagram shown in Fig. 6 is general and represents guidelines on how the algorithm can be easily implemented in a more specific device (such as an FPGA or an industrial controller).
The developed SVPWM is verified experimentally. As mentioned, real-time platform dSpace ds1006 was used for implementation. The general view of the experimental setup is shown in Fig. 7. A custom made NPC inverter is used to drive a symmetrical six-phase induction machine, which operates at no-load. The inverter is supplied by a dc-bus voltage, Vdc of 200 V, provided from the external dc source Sorensen SGI 600/25. Dead time of the inverter is 6 μs, and the used switching frequency is, fsw = 2 kHz. The machine parameters are listed in Table III. The machine is controlled using V/f where at 50 Hz (i.e., machine's rated frequency) the chosen peak voltage of the phase voltage reference space vector V* = 100 V is obtained. This is equivalent to the modulation index mi = 1, since modulation index mi is defined as:

Sub-sector Condition
Ak This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. It should be noted that the experimental validation is done in open loop and the inverter dead time is not compensated in any way. The measurements for the full linear range of the modulation index (i.e. from mi = 0.1 to 1) with 0.05 increments are taken when the machine has reached steady state speed using Tektronix P5205A and TCP0030A probes connected to Tektronix DPO2014B oscilloscope.
The carrier-based modulation strategy with PD-PWM is also developed and used for comparison. The equivalence of the SVPWM and carrier-based algorithms has been verified so far for 3-, 5-and 7-phase three-level converters [16,2,3]. Hence, the same result is expected here. The only difference is that in [16,2,3] respective PD-PWM algorithms took into consideration sinusoidal references with double min-max injection. However, in the case of a symmetrical six-phase machine, there is a symmetry of the sinusoidal signals and application of min-max injection is not possible. More precisely, application of the min-max or double min-max injection will not change the shape of the reference signals. That means that in the case of a six-phase symmetrical machine, the developed SVPWM technique is compared with a simple carrier-based PWM (CBPWM) with sinusoidal references (without any harmonic injection). The orientation of the carriers in level shifted zones is in-phase disposition PD-PWM, as already mentioned.
The validity of the developed algorithms can be established by analysing the experimentally acquired waveforms. For example, the experimental results when mi = 0.4 and mi = 1, for the developed SVPWM algorithm and PD-PWM, are shown in Fig. 8 and Fig. 9, respectively. One can clearly see that the value of fundamental phase voltage, obtained using the developed algorithm, is very close to the value of the fundamental reference (40 V in Fig. 8 i.e. 100 V in Fig. 9). Here, one can see that the influence of the dead time on the value of fundamental is more expressed for the lower than for the higher modulation indices, as there are more switching periods within a fundamental period (as noted, dead-time compensation was not used). Further, one can see that the low order harmonics are present, albeit of very small magnitude in both phase voltage and current harmonic spectra (see Figs. 8 and 9, c and d). Ideally, the low order harmonics should not exist. In reality, this is not the case and the dominant low order harmonics are the third, fifth and ninth harmonics. This is expected since the dead time is not compensated and it leads to the appearance of low order odd harmonics in the phase voltage waveform [21]. Moreover, the largest odd harmonic caused by the dead time (the third harmonic) maps into the 0axis, where the impedance is very low, since it consists of only stator resistance and leakage inductance. The impedance in the α-β plane, where the fifth harmonic maps, is much higher. As a result, this contributes to the large third stator current harmonic, as can be seen from the phase current harmonic spectra plots.
By comparing Fig. 8 and Fig. 9, it is obvious that the developed algorithm yields similar results to PD-PWM. It should be noted that this is also valid for the full linear range of mi. In order to validate this claim, phase voltage and current total harmonics distortion (THD) of both modulation strategies is calculated using:  (9) as THD is the most suitable indicator in determining the performance of the modulation strategy applied to multiphase drives [22]. The Vk and Ik represent the k-th components of the phase voltage and current in the spectrum, while V1 and I1 are the fundamental values of phase voltage and current, respectively. Harmonic components up to h = 420 (21 kHz), i.e. the first ten sidebands, are included in both THD calculations. The calculated phase 'a' THDv and THDi of both modulation strategies for the full linear range of mi are shown in Fig. 10 and Fig. 11, respectively. For the comparison purposes simulation of the system has been implemented in Matlab/Simulink. The same parameters as in the experiment were used. Dead time was also considered in the simulations. One can clearly see in Fig. 10 that THDv of both modulation strategies, either from simulation or experiment, are identical to each other. Moreover, the results are also in agreement with the analytically calculated THDv presented in [22]. Likewise, in Fig. 11, THDi of both modulation strategies yield the same results. However, THDi from the experimental results shows much higher values compared to THDi from the simulation results. Yet, the shapes of both THDi curves are similar and the experimental ones appear as having a vertical, almost constant, shift with respect to the simulation ones. The  difference between them is due to the assumption made in the development of the machine model where the rotor leakage inductance is assumed constant for all switching harmonics; in reality, this is not the case [23]. Finally, the algorithms are compared based on the execution time. The execution time of the algorithms has been measured using dSpace Profiler Tool. The execution time of the developed CBPWM is 0.6 µs. The execution time of the initial implementation of SVPWM algorithm was 10 µs (the switching sequences for all sub-sectors in S1 and S2 were stored in the memory). It has been significantly reduced to 4 µs, when the corresponding inverted matrices for dwell time calculation from (6), were stored in the memory as well.

IV. CONCLUSION
In this paper, a space vector algorithm based on VSD approach for three-level six-phase NPC inverter driving a symmetrical six-phase induction machine with a single isolated neutral point is presented. The steps for determining and applying switching sequences required to obtain sinusoidal phase voltage waveforms are explained in detail. Although the steps are quite complex, only two of those steps are essential for final development and real-time implementation of the presented algorithm. The developed algorithm is evaluated using simulation in Matlab/Simulink environment and validated experimentally. Obtained results show that the algorithm achieves desired fundamental voltage. Low order harmonics, observed in the output voltages and currents, are due to the uncompensated inverter dead time. In addition, the results are also identical with the results obtained from PD-PWM with pure sinusoidal references. The validity of the developed SVPWM algorithm is proven further based on the comparison of calculated voltage and current THD values for both simulation and experimental results, including the results obtained with PD-PWM for the full linear range of the modulation index. These show that they yield the same performance.   This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.