Ji, Z (2015) SrTiO3 for sub-20 nm DRAM technology nodes — characterization and modeling. In: Microelectronic Engineering , 147 (C). pp. 126-129. (IEEE Semiconductor Interfaces Specialist Conference, 1st - 5th December 2014, San Diego, CA).

Preview

Text infos2015_v0[1].pdf Available under License Creative Commons Attribution Non-commercial No Derivatives. Download (1MB) | Preview

Abstract

The electrical properties of Ru/SrTiOx/Ru capacitors have been investigated. Equivalent Oxide Thickness (EOT) of 0.38 nm at 0 V and current density of 10−7 A cm−2 at ±1 V and 25 °C meet the sub-20 nm DRAM requirements. Relaxation measurements were performed, indicating acceptable charge loss. Modeling of charge trapping at defect sites based on multi-phonon trap-assisted-tunneling quantitatively well describes leakage and capacitance behavior.

Item Type:	Conference or Workshop Item (Paper)
Subjects:	T Technology > TK Electrical engineering. Electronics. Nuclear engineering
Divisions:	Electronics & Electrical Engineering (merged with Engineering 10 Aug 20)
Publisher:	Elsevier
Date Deposited:	09 Oct 2015 12:43
Last Modified:	13 Apr 2022 15:14
URI:	https://researchonline.ljmu.ac.uk/id/eprint/2148

View Item