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Understanding charge traps for optimizing Si-passivated Ge nMOSFETs

Ji, Z, Gao, R, Zhang, JF, Zhang, WD, Duan, M, Ren, P, Arimura, H, Wang, R and Franco, R (2016) Understanding charge traps for optimizing Si-passivated Ge nMOSFETs. In: 2016 IEEE Symposium on VLSI Technology . (Symposia on VLSI Technology and Circuits, 13th-17th June 2016, Hawaii, US).

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Ge is an attractive channel material offering high hole and electron mobility, and therefore of interest for future p- and n-FET technologies. Ge nFETs can be made through two routes: GeO2/high-k directly on Ge [1] or using a Si-passivated monolayer (ML) [2]. The former offers higher mobility but poor reliability [3], while the Si-passivated option has a better balance between mobility and reliability, making it promising for the debut of Ge CMOS [4]. However, significant trapping-induced PBTI compared with the Si counterpart is the key hurdle for its practical use. To optimize it, there is a pressing need for understanding the properties of these traps as well as their impact on time-dependent mobility and reliability. In this work, for the first time, two types of electron traps are unambiguously identified in Ge nFETs, which are controlled respectively by a) the HK layer thickness and b) the growth conditions used for the Si-passivated layer. These different traps exhibit different impacts on mobility degradation. Based on this, process is improved, as experimentally verified with maximum operation overdrive enhanced by a factor of ~1.7 (4&6ML)

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering
Divisions: Electronics & Electrical Engineering (merged with Engineering 10 Aug 20)
Publisher: IEEE
Date Deposited: 21 Mar 2016 10:25
Last Modified: 13 Apr 2022 15:14
URI: https://researchonline.ljmu.ac.uk/id/eprint/3297
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