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Development of characterization techniques for negative bias temperature instabilities

Lin, L (2012) Development of characterization techniques for negative bias temperature instabilities. Doctoral thesis, Liverpool John Moores University.

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The requirements for ever faster circuits and higher packing density have driven the continuous downscaling of the transistor sizes in the last 50 years or so. This leads to higher electrical field and operation temperature and, in turn, accelerates the degradation. One of the most serious reliability issues for the current CMOS technology is the negative bias temperature instability (NETI). This project will focus on investigating the NBTI and the positive charges responsible for it. Modem MOSFETs use gate dielectrics in the nanometer range and the degradation will recover rapidly. To suppress the recovery, high speed characterization technique is needed. In this project the measurement speed has been improved from Sus to 200 ns for Id-Vg measurements and 800ns for C- V measurement. As a Hf-dielectric/SiON stack is replacing SiON as the gate dielectric, the task is to identify which layer of the stack dominates positive charging (PC). A main achievement in this project is the finding that PCs are dominated by the interfacial layer (IL) and they do not pile up at the HfSiON/(IL) interface. Evaluating the conventional threshold voltage shift measured by extrapolating transfer characteristics, ? Vth( ex), underestimates the NBTI-induced degradation of drain current, ?ld. In this project we proposed the effective threshold voltage shift, ? Veff, in order to evaluate the devices degradation correctly. The next task was to develop a lifetime prediction method, based on ?Veff. To predict the worst-case lifetime which is recovery free, a model for NBTI kinetics under operation gate bias was developed. This kinetics includes contributions from both as-grown and generated defects and it no longer follows a simple power law. Based on the new kinetics, a single test prediction method was proposed and its safety margin is estimated to be 50%. A fast single pulse charge pumping (SPCP) technique was developed in this project, reducing the measurement time to microseconds. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained and their saturation level is used to evaluate interface states. For the first time, SPCP allows the recovery of interface states to be monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100?s, which would be missed if conventional charge pumping were used.

Item Type: Thesis (Doctoral)
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering
Divisions: Electronics & Electrical Engineering (merged with Engineering 10 Aug 20)
Date Deposited: 29 Mar 2017 09:46
Last Modified: 03 Sep 2021 23:30
URI: https://researchonline.ljmu.ac.uk/id/eprint/6108
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