Zheng, X, Wang, Z, Li, F, Zhao, F, Yue, S, Zhang, C and Wang, Z (2016) A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process. IEEE Transactions on Circuits and Systems I: Regular Papers, 63 (9). pp. 1381-1392. ISSN 1549-8328

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Abstract

This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

Item Type:	Article
Uncontrolled Keywords:	0906 Electrical And Electronic Engineering
Subjects:	Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions:	Computer Science & Mathematics
Publisher:	IEEE
Date Deposited:	23 Oct 2018 09:29
Last Modified:	04 Sep 2021 03:49
DOI or ID number:	10.1109/TCSI.2016.2580703
URI:	https://researchonline.ljmu.ac.uk/id/eprint/7196

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