Voltage step stress: a technique for reducing test time of device ageing

Zhang, JF, Ji, Z, Duan, M, Zhang, WD and Zhao, C (2019) Voltage step stress: a technique for reducing test time of device ageing. In: 2019 International Conference on IC Design and Technology (ICICDT) . (THE 17th INTERNATIONAL CONFERENCE ON IC DESIGN & TECHNOLOGY, 17 - 19 June 2019, Suzhou, China).

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Abstract

Device ageing leads to circuit malfunction and must be controlled. During ageing, defects build up slowly and the test is time consuming and costly. The typical ageing tests are repeated ~5 times under different voltages. To reduce the test time, the voltage step stress (VSS) technique is proposed, which replaces the multiple tests under different voltage by a single test and saves time. This paper reviews the recent development of the VSS technique. After presenting its underlying principle, its applicability will be demonstrated for both the negative bias temperature instability and hot carrier ageing.

Item Type:	Conference or Workshop Item (Paper)
Subjects:	T Technology > TK Electrical engineering. Electronics. Nuclear engineering
Divisions:	Electronics and Electrical Engineering (merged with Engineering 10 Aug 20)
Publisher:	IEEE
Date of acceptance:	14 June 2019
Date of first compliant Open Access:	1 October 2019
Date Deposited:	18 Jul 2019 11:28
Last Modified:	13 Apr 2022 15:17
URI:	https://researchonline.ljmu.ac.uk/id/eprint/11066

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