Brown, J, Zhang, JF, Zhou, B, Mehedi, M, Freitas, P, Marsland, J and Ji, Z (2020) Random‑telegraph‑noise‑enabled true random number generator for hardware security. Scientific Reports, 10. ISSN 2045-2322

Preview

Text Random‑telegraph‑noise‑enabled true random number generator for hardware security.pdf - Published Version Available under License Creative Commons Attribution. Download (2MB) | Preview

Abstract

The future security of Internet of Things is a key concern in the cyber-security field. One of the key issues is the ability to generate random numbers with strict power and area constrains. “True Random Number Generators” have been presented as a potential solution to this problem but improvements in output bit rate, power consumption, and design complexity must be made. In this work we present a novel and experimentally verified “True Random Number Generator” that uses exclusively conventional CMOS technology as well as offering key improvements over previous designs in complexity, output bitrate, and power consumption. It uses the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source. For the first time multilevel and abnormal telegraph noise can be utilised, which greatly reduces device selectivity and offers much greater bitrates. The design is verified using a breadboard and FPGA proof of concept circuit and passes all 15 of the NIST randomness tests without any need for post-processing of the generated bitstream. The design also shows resilience against machine learning attacks performed by the LSTM neural network.

Item Type:	Article
Subjects:	Q Science > QA Mathematics > QA75 Electronic computers. Computer science T Technology > T Technology (General)
Divisions:	Civil Engineering & Built Environment Computer Science & Mathematics
Publisher:	Nature Publishing Group
Date Deposited:	16 Oct 2020 09:56
Last Modified:	04 Sep 2021 06:34
DOI or ID number:	10.1038/s41598-020-74351-y
URI:	https://researchonline.ljmu.ac.uk/id/eprint/13796

View Item