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Device and Circuit Performance of the Future Hybrid III-V and Ge-Based CMOS Technology

Benbakhti, B and Chan, KH and Soltani, A and Kalna, K (2016) Device and Circuit Performance of the Future Hybrid III-V and Ge-Based CMOS Technology. IEEE Transactions on Electron Devices, 63 (10). pp. 3893-3899. ISSN 0018-9383

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Abstract

The device and circuit performance of a 20-nm gate length InGaAs and Ge hybrid CMOS based on an implant free quantum well (QW) device architecture is studied using a multiscale approach combining ensemble Monte Carlo simulation, drift-diffusion simulation, compact modeling, and TCAD mixed-mode circuit simulation. We have found that the QW and doped substrate, used in the hybrid CMOS, help to reduce short-channel effects by enhancing carrier confinement. The QW also reduces the destructive impact of a low density of states in III-V materials. In addition, the calculated access resistance is found to be a much lower than in Si counterparts thanks to a heavily doped overgrowth source/drain contact. We predict an overall low gate capacitance and a large drive current when compared with Si-CMOS that leads to a significant reduction in a circuit propagation time delay (∼5.5 ps). © 1963-2012 IEEE.

Item Type: Article
Uncontrolled Keywords: 0906 Electrical And Electronic Engineering
Subjects: T Technology > TK Electrical engineering. Electronics. Nuclear engineering
Divisions: Electronics and Electrical Engineering
Publisher: IEEE
Date Deposited: 09 Nov 2016 11:38
Last Modified: 07 Sep 2017 17:26
DOI or Identification number: 10.1109/TED.2016.2603188
URI: http://researchonline.ljmu.ac.uk/id/eprint/4771

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